1. Field of the Invention
An embodiment of the present invention relates to microelectronic device fabrication. In particular, embodiments of the present invention relate to methods of fabricating interconnects with capping layers that include sealing structures to improved encapsulation of the interconnects.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased integrated circuit density and complexity, and equally dramatic decreases in package size. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. These transistors are generally connected to one another and/or to devices external to the microelectronic device by conductive traces and vias (hereinafter collectively referred to “interconnects”) through which electronic signals are sent and/or received.
One process used to form interconnects is known as a “damascene process”. In a typical damascene process, as shown in FIG. 17, a photoresist material 202 is patterned on a first dielectric material layer 204, which is etched through the photoresist material 202 patterning to form a hole or trench 206 extending to at least partially through the first dielectric material layer 204, as shown in FIG. 18. The photoresist material 202 is then removed (typically by an oxygen plasma) and a barrier layer 208 is deposited within the hole or trench 206 on sidewalls 210 and a bottom surface 212 thereof to prevent conductive material (particularly copper and copper-containing alloys), which will be subsequently deposited into the hole or trench 206, from migrating into the first dielectric material layer 204, as shown in FIG. 19. The migration of the conductive material can adversely affect the quality of microelectronic device, such as leakage current and reliability between the interconnects, as will be understood to those skilled in the art. The barrier layer 208 used for copper-containing conductive materials are usually nitrogen-containing materials, including, but not limited to tantalum, tantalum nitride, titanium, titanium nitride, and ruthenium. The deposition of the barrier layer 208 usually results in a portion of the barrier layer 208 extending on a first surface 214 of the first dielectric material layer 204.
As shown in FIG. 20, a seed material 216 may be deposited on the barrier layer 208. The hole or trench 206 is then filled, usually by an electroplating process, with the conductive material (e.g., such as copper and alloys thereof), as shown in FIG. 21, to form a conductive material layer 218. Like the barrier layer 208, excess conductive material may form proximate the first dielectric material layer first surface 214. The resulting structure is planarized, usually by a technique called chemical mechanical polish (CMP), which removes the portion conductive material layer 218 and barrier layer 208 that is not within the hole or trench 206 (see FIG. 19) from the surface first dielectric material first surface 214, to form the interconnect 222, as shown in FIG. 22.
As shown in FIGS. 23 and 24, the interconnect 222 is then capped with a capping layer 224 including, but not limited to, cobalt and alloys thereof. The capping layer 224 may be formed by any method known in the art, including plating techniques. The capping layer 224 prevents the electromigration and/or diffusion of the conductive material of the interconnect 222 into a subsequently deposited second dielectric material layer (not shown), which is deposited over the first dielectric material layer 204 and capping layer 224.
A selective deposition process, such as electroless plating, is a standard industry approach for forming the capping layer 224 due to its process simplicity. However, one of the challenges of selective processes is their sensitivity to surface contamination, oxidation, and/or poor deposition (particularly with copper interconnects), which results in process marginality. Furthermore, current interconnect structures may not provide sufficient encapsulation of the conductive material of the interconnects. For example, referring to back to FIGS. 23 and 24, the area of confluence 230 of the capping layer 224 and the barrier layer 208 (shown within the dashed circle) can provide insufficient coverage to prevent the conductive material of the interconnect 222 from electromigrating and/or diffusing into surrounding dielectric and devices through the gap between the capping layer 224 and the barrier layer 208.
Therefore, it would be advantageous to develop a method to form a capped interconnect having improved encapsulation.